Decoupling Capacitor Placement Calculator

Different capacitor values are effective at different frequencies. Large capacitors (10-100µF) handle low frequency noise and power transients, while small capacitors (10-100nF) filter high frequency switching noise. Using multiple values creates a broader frequency response.

C0G (NP0) capacitors have excellent stability and low losses but limited to smaller values. X7R capacitors offer higher capacitance values but have more variation with temperature and voltage. For critical decoupling, C0G is preferred for small values, X7R for larger ones.

Decoupling capacitors should be placed as close as possible to the power pins, ideally within 5mm. The trace length creates inductance that reduces filtering effectiveness at high frequencies. Via placement should also minimize loop area.

Use the formula C = 1/(2π × f × Z) where f is the target frequency and Z is desired impedance. For digital circuits, start with 100nF for frequencies around 100MHz and add larger values (1-10µF) for lower frequency filtering.

For solid power planes, place capacitors near IC power pins with short vias. For split planes, add extra capacitors at plane boundaries. Multi-layer boards allow better power distribution, reducing the number of capacitors needed compared to 2-layer designs.

Generally, use one 100nF ceramic capacitor per power pin pair, plus one larger bulk capacitor (1-10µF) per IC. High-speed or high-current ICs may require additional capacitors of different values to cover a broader frequency range.

Insufficient decoupling can cause power supply noise, signal integrity issues, increased EMI, and circuit malfunction. Digital circuits may experience timing errors, while analog circuits can suffer from reduced performance and increased noise.

Smaller packages (0402, 0603) have lower parasitic inductance and are better for high-frequency decoupling. Larger packages (0805, 1206) can handle higher currents and voltages. Choose based on frequency requirements and current handling needs.